The present invention relates in general to semiconductor power field effect transistors (FETs), and more particularly to a method and structure for forming a minimum pitch trench-gate FET with heavy body regions.
A cross-sectional view of a conventional trench-gate power MOSFET 10 is shown in FIG. 1. MOSFET 10 includes an n-type substrate 101 on which an n-type epitaxial layer 102 is grown. Substrate 101 embodies the drain of MOSFET 10. A p-type body region 108 extends into epitaxial layer 102. Trenches 113 extend through body region 108 and into the portion of epitaxial layer 102 bounded by body region 108 and substrate 101 (commonly referred to as the drift region). A gate dielectric layer 131 is formed on the sidewalls and bottom of each trench 113. Source regions 110 flank trenches 131. Heavy body regions 137 are formed within body region 108 between adjacent source regions 110. Gate electrodes 132 (e.g., from polysilicon) fill trenches 131 and embody the gate of MOSFET 10. Dielectric cap 133 covers trenches 113 and also partially extends over source regions 110. A top-side metal layer 139 electrically contacts source regions 110 and heavy body regions 137. A bottom-side metal layer (not shown) contacts substrate 101.
To increase the transistor packing density, it is desirable to minimize the trench width as well as the mesa width (i.e., the spacing between adjacent trenches). However, both of these dimensions are limited by constraints imposed by manufacturing equipment, structural requirements, misalignment tolerances, and transistor operational requirements. For example, the minimum width of the mesa region between adjacent trenches 113 in FIG. 1 is limited by the space required for forming source regions 110 and heavy body regions 137. Misalignment tolerances associated with forming heavy body regions 137 further increase the mesa width.
Many techniques for reducing the cell pitch of trench-gate FETs have been proposed, but none have been able to achieve a substantial reduction in the cell pitch without significantly complicating the manufacturing process. For example, one method for reducing the cell pitch has been the use of spacers to obtain self-aligned features. However, this method requires additional process steps to form and then remove the spacers. Further, the spacer method involves etching of silicon to obtain recessed heavy body regions. The process steps associated with etching silicon and repairing the damaged silicon surfaces further complicates the manufacturing process.
Thus, there is a need for a technique whereby the cell pitch of trench-gate FETs can be significantly reduced while maintaining a simple manufacturing process.